Research Interests

Logic Synthesis, Digital Design, Programmable Devices

Artificial Intelligence, Multiple Valued Functions

Digital Signal Processing, Bio-medical Image Processing

Networks, Path Planning

 

Graduate Supervision

·         Ph.D.:

1.      Venkatesan Muthukumar 1997-2000, New Approaches for Partition based Functional Decomposition, Supervisor -1997-1998 and Co-supervisor 1999-2000, (Associate Prof., UNLV, USA).

2.      Bing Li: 1999-2000 (incomplete)

3.      Ling Wang: 2001–2003, Scheduling and Partitioning VLSI Circuit Operating at Multiple Supply Voltages, (Associate Prof., Harbin Institute of Technology, China).

4.      Abdul Bhuiyan, 2005-2009, Analysis and Design of Low Power CMOS Ultra Wideband Receiver, (NIH, USA).

5.      Dawid Zydek, August 2007 - March 2010, Processor Allocator for Chip Multiprocessors, (Assistant Professor, Idaho State University).

6.      Grzegorz Chmaj, August 2011 – June 2016.

  1. Saugath Sharma August 2018 – till date

 

 

·         MSEE:

1.      Venkatesan Muthukumar: Parallel Decomposition of Binary Valued Functions, March, 1997.

2.      J. Feng: Coding MCCs in Functional Decomposition for FPGA-based Design, December, 1999.

3.      N. Dhavlikar: Partitioning Large VLSI Designs, April 2001.

4.      G. Cherussery: Reconfigurable Designs, December 2002.

5.      Utthaman Thirunavukarasu, Analysis of Runtime Re-Configuration Systems, January 2003 –  August, 2005.

6.      Thomas Kiesling, Dec., 2005.

7.      Avinash Ramani, Decomposition Tool Targeting FPGA Architectures, April, 2007.

8.      Vikram Mylaram, August, 2008.

9.      Nachiket Jugade, Implementation of BMA Based Motion Estimation Hardware Accelerator In HDL, August, 2008.

10.  Arun Kumar Reddy Toomu, Pipelined Implementation of JPEG Image Compression Using VHDL, August, 2008.

11.  Ramaskrishna Yadav Gopalakrishnan, Implementation of JPEG Compression and Motion Estimation on FPGA Hardware, August, 2008.

12.  Arpita Kadakia, Data Routing in Multicore Processors Using Dimension Increment Method, December, 2010.

13.  Bartosz Kajak, Path Planning, August 2011.

14.  Rana Sangaram Reddy, September 2012.

15.  Bartosz Duszel, August 2011 – November 2013.

16.  Libymol Abraham, 2016.

17.  Nikita Wanjale April 2017.

List of Publications

Books and Major Thesis

 

1.      Proceedings of the 27th International Conference on Systems Engineering 2020, Springer Lecture Notes in Networks and Systems, vol. 182, Edited by H Selvaraj, G Chmaj. D Zydek, ISBN 978-3-030-65795-6, Dec. 2020.

2.      Proceedings 25th International Conference on Systems Engineering ICSEng 2017, IEEE Computer Society Edited by Selvaraj, H., Chmaj, G., & Zydek, D. ISBN-13: 978-1-5386-0610-0, 2017.

3.      Progress in Systems Engineering: Proceedings of the Twenty-third International

Conference on Systems Engineering, Springer, Edited by H. Selvaraj, D. Zydek, G. Chmaj, ISBN 978-3-319-08421-3, 2014.

4.      Proceedings, International Conference on Systems Engineering, 2011, IEEE Computer Society, Edited by H. Selvaraj, D. Zydek, ISBN 978-0-7695-4495-3, 2011

5.      Proceedings, International Conference on Systems Engineering, 2008, IEEE Computer Society, Edited by H. Selvaraj, M. Rawski, ISBN 978-0-7695-3331-5, 2008

6.      Proceedings, International Conference on Computational Intelligence and Applications, 2007, Edited by H. Selvaraj, B. Verma, IEEE Computer Society, ISBN 0-7695-3050-8, vol. 4, 2007

7.      Reconfigurable Embedded Systems: Synthesis, Design and Application, Special Issue, Journal of Systems Architecture,, ELSEVIER, Edited by H. Selvaraj, L. Jozwiak, ISSN 1383-7621, vol. 51, no. 6-7, June-July, 2005

8.      Proceedings, International Conference on Computational Intelligence and Multimedia Applications, 2005, IEEE Computer Society, Edited by H. Selvaraj, B. Verma, A. Carvalho, ISBN 0-7695-2358-7, 2005

9.      Proceedings, Eighteenth International Conference on Systems Engineering, Las Vegas, NV, USA, IEEE Computer Society, Edited by H. Selvaraj, V. Muthukumar, ISBN 0-7695-2359-5, August 16-18, 2005

10.  Proceedings, IEEE International Conference on Information Technology, Las Vegas, NV, USA, IEEE Computer Society, Edited by H. Selvaraj, P.K. Srimani, ISBN 0-7695-2315-3, April 4-6, 2005

11.  Proceedings, ICSE-INCOSE joint conference on Synergy Between Systems Engineering and Project Management - Edited by H. Selvaraj and V. Muthukumar, 2004, Omni Press, Edited by H. Selvaraj, V. Muthukumar, 2004

12.  Proceedings, Euromicro DSD’04, 2004, IEEE Computer Society, Edited by H. Selvaraj, ISBN 0-7695-2003-0, 2004

13.  Proceedings, International Conference on Computational Intelligence and Multimedia Applications, 2003, IEEE Computer Society, Edited by L. Jiao, H. Selvaraj, B.Verma, X. Yao, ISBN 0-7695-1957-1, 2003

14.  Proceedings, Euromicro DSD’03, 2003, IEEE Computer Society, Edited by H. Selvaraj, ISBN 0-7695-2003-0, 2003

15.  Design of Intelligent Agents, Special Issue, International Journal of Computational Intelligence and Applications, Imperial College Press, Edited by H. Selvaraj, ISSN 1469-0268, vol. 2, no. 4, December, 2002

16.  Proceedings, Fifteenth International Conference on Systems Engineering, Omni Press, Edited by H. Selvaraj, V. Muthukumar, 2002

17.  Proceedings, International Conference on Computational Intelligence and Multimedia Applications, IEEE Computer Society, Edited by B. Verma, A. Namatame, X. Yao, H. Selvaraj, A. de Carvalho, A. Ohuchi, ISBN 1-930708-29-7, 2001

18.  Proceedings, International Conference on Computational Intelligence and Multimedia Applications, 1999, IEEE Computer Science Press, Edited by B. Verma, H. Selvaraj, Andrei Carvalho, Xin Yao, ISBN 981-02-2306-4, 1999

19.  Proceedings, International Conference on Computational Intelligence and Multimedia Applications, 1998, World Scientific, Edited by H. Selvaraj, B. Verma, ISBN 981-02-3352-3, 1998

20.  Poster Proceedings, International Conference on Computational Intelligence and Multimedia Applications, 1998, Monash University, Edited by H. Selvaraj, B. Verma, M. Mohammadian, 1998

21.  Design and Comparative Analysis of Czebyszew Digital Filters Using Integrators, Warsaw University of Technology, 1986

22.  FPGA-Based Logic Synthesis, Warsaw University of Technology, 1994

 

Monographs or Scripts

1.      H. Selvaraj, Data Communication and Computer Networks II, Monash University, Australia, 1998.

2.      H. Selvaraj, Computer Organization, Monash University, Australia, 1996, revised 1997.

3.      T. Roberts, H. Selvaraj, Artificial Intelligence, Monash University, Australia, 1997.

4.      M. Hassan H. Selvaraj, Data Communications, Monash University, Australia, 1995.

 

Book Chapters

1.      M. Rawski, H. Selvaraj, T. Luba: Pattern Recognition Technologies and Applications: Recent Advances, Chapter XII, Information Science Reference, ISBN-13: 978-1-59904-807-9 (hardcover), ISBN-13: 978-1-59904-807-3 (e-book); pp. 265-283, 2008

  1. Chapter 10 titled “Balanced multilevel decomposition and its applications in FPGA-based synthesis” by T. Luba, H. Selvaraj, M. Nowicka, A. Krasniewski in the book “Logic and Architecture Synthesis, State-of-the-art and novel approaches” Edited by Gabriele Saucier and Anne Mignotte, Chapman & Hall, ISBN 0-41272-690-4, pp.109-115, 1995
  2. P. Sapiecha, H. Selvaraj, M. Pleban, Rough Sets and Current Trends in Computing, Springer, Edited by W. Ziarko, Y. Yao; ISBN 3-540-43074-1, pp. 487-494

 

Invited Conference Papers

  1. L. Gewali, H. Selveraj, D. Mazzella, Constrained Disjoint Paths in Geometric Network, Proceedings of the International Conference on Computational Intelligence and Multimedia Applications, 2007, IEEE CS, ISBN 0-7695-3050-8, pp. xxiii-xxx
  2. H. Selvaraj, M. Nowicka, T. Luba, Non-Disjoint Decomposition Strategy in Decomposition-Based Algorithms and Tools, ICCIMA’98, Monash University, Australia, World Scientific, ISBN 981-02-3352-3, 1998

3.      H. Selvaraj, T. Luba, M. Nowicka, B. Bignall, Multiple-valued Decomposition and its Applications in Data Compression and Technology Mapping, Invited Paper, International Conference on Computational Intelligence and Multimedia Applications, Griffith University, Australia - 1997.

 

Refereed Journal articles

1.      Chmaj, G., Selvaraj, H. (2016). Energy-Efficient Computing Solutions for Internet of Things with ZigBee Reconfigurable Devices. International Journal of Software Innovation, 4(1), pp.31-47. www.igi-global.com/article/energy-efficient-computing-solutions-for-internet-of-things-with-zigbee-reconfigurable-devices/144140.

2.      D. Selvathi, H. Selvaraj, J. Dharani, FPGA Implementation of Fuzzy Inference System Based Edge Detection Algorithm, International Journal of Computational Intelligence and Applications; Vol. 14; Issue 02; pp1550009-1 to1550009-21, ISSN: 1469-0268, 2015.

3.      D. Selvathi, N. Emimal, and Henry Selvaraj, Automated Characterization of Atheromatous Plaque in Intravascular Ultrasound Images Using Neuro Fuzzy Classifier, International Journal of Electronics and Telecommunications, 2012, vol. 58, no. 4, pp. 425–431.

4.      T. Moazzeni, Y. Jiang, H. Selvaraj and T. Chen, Analytical Models for Distribution of Envelope and Phase of Linearly Modulated Signals in AWGN Channel, International Journal of Electronics and Telecommunications, 2014, vol. 60, no. 1, pp. 79-82. DOI: 10:24.278/eletel-2014-0008.

5.      D. Selvathi, N. Emimal, H. Selvaraj, Automated Characterization of Atheromatous Plaque in Intravascular Ultrasound Images using Neuro Fuzzy Classifier, International Journal of Electronics and Telecommunication, vol. 58, no. 4, pp. 425-432, 2012

6.      D. Zydek, G. Chmaj, A. Shawky, H. Selvaraj, Location of Processor Allocator and Job Scheduler and Its Impact on CMP Performance, International Journal of Electronics and Telecommunications, vol. 58, no. 1, pp. 9-14, 2012, doi: 0.2478/v10177-012-0001-y

7.      T. Czyz, R. Rudek, H. Selvaraj, Parallel Computation Approaches to Optimize Learning Systems, International Journal of Electronics and Telecommunication, vol. 57, no. 2, pp. 223-228, 2011

8.      G. Wiselin jiji, H. Selvaraj, G.Evelin Suji, Supervised Classification of White Blood Cells by Fusion of Color Texture Features and Neural Network, International Journal of Computational Intelligence and Applications, World Scientific Publishing Company, 2011

9.      D. Zydek, H. Selvaraj, Fast and Efficient Processor Allocation Algorithm for Torus-Based Chip Multiprocessors, Computers & Electrical Engineering, vol. 37, issue 1, pp. 91-105, 2011

10.  D. Zydek, H. Selvaraj, G. Borowik, T. Luba, Energy characteristic of a processor allocator and a network-on-chip, International Journal of Applied Mathematics and Computer Science, ISSN 1641-876x, vol. 21, no. 2, pp. 385-399, 2011

11.  D. Zydek, H. Selvaraj, L. Koszalka, I. Pozniak-Koszalka, Evaluation Scheme for NoC based CMP with Integrated Processor Management System, International Journal of Electronics and Telecommunication, vol. 56, no. 2, pp. 157-168, 2010

12.  D. Zydek, H. Selvaraj, Hardware Implementation of Processor Allocation Schemes for Mesh-Based Chip Multiprocessors, Journal of Microprocessors and Microsystems, vol. 34, no. 1, pp. 39-48, 2010

13.  T. Moazzeni, H. Selvaraj, Y. Jiang, A Novel Multi-Exponential Function-based Companding Technique for Uniform Signal Compression over Channels with Limited Dynamic Range, International Journal of Electronics and Telecommunications, vol. 56, no. 2, pp. 125-128, June 2010

14.  A.K. Mandava, E.E.Regentova, H.Selvaraj, Real-time on-board object tracking for cooperative flight control, Systems Science, vol.36, no. 2, pp.15-22., 2010

15.  A.R.N.B. Kamal, S. T. Selvi, H. Selvaraj, Enhanced Iteration-Free Fractal Image Coding Algorithm with Efficient Search and Storage Space, International Journal of Image and Graphics, submitted for publication, 2009

16.  D. Selvathi, H. Selvaraj, S. Tamarai Selvi, Hybrid Approach for Brain Tumor Segmentation in Magnetic Resonance Images using Cellular Neural Networks and Optimization Techniques, International Journal of Computational Intelligence and Multimedia Applications, Imperial College Press, vol. 9, no. 1, pp17-31, 2010, doi: 10.1142/S1469026810002781

17.  L. Gewali, D. Mazzilla, H. Selvaraj, Constraint Disjoint Paths in Geometric Network, International Journal of Computational Intelligence and Multimedia Applications, vol.8, no. 2, pp. 141-154, 2009

18.  M. Yang, H. Selvaraj, E. Lu, J. Wang, S.Q. Zheng, Y. Jiang, Scheduling Architectures for DiffServ Networks with Input Queuing Switches, Electronics and Telecommunications Quarterly, vol. 55, no 1, pp 9-30, 2009

19.  Gewali L., Rongatana N., H. Selvaraj, Pedersen J.B., Free Regions of Sensor Nodes, International Journal of System Sciences, vol. 35, no.2, pp 67-72, 2009

20.  P. Szotkowski, M. Rawski, H. Selvaraj, A graph-based approach to symbolic functional decomposition of finite state machines, International Journal of System Sciences, vol. 35, no. 2, pp. 41-48, 2009

21.  A.R.N.B. Kamal, S. T. Selvi, H. Selvaraj, Iteration-Free Fractal Coding for Image Compression using Genetic Algorithm, International Journal of Computational Intelligence and Multimedia Applications, vol. 7, no. 4, pp. 429-446, December 2008

22.  H. Selvaraj, S. Thamarai Selvi, D. Selvathi, L. Gewali, Brain MRI Slices Classification Using Least Squares Support Vector Machine, International Journal of Intelligent Computing in Medical Sciences, pp. 21-33, 2007

23.  V. Muthukumar, R.J. Bignall, H. Selvaraj, An efficient variable partitioning approach for functional decomposition of circuits, Journal of System Architecture (JSA), NY, USA, ISSN 1383-7621, vol. 53, no. 1, pp. 53-67, 2007

24.  D. Wen, L. Wang, Y. Jiang, H. Selvaraj, X. Yang, Placement-Directed Behavioral Synthesis for Multiple Voltage VLSI Designs with Simultaneous Scheduling, Binding, and Partitioning, International Journal of Computers and Their Applications, vol. 14, no. 2, pp. 92-98, June 2007

25.  Wang L., Y. Jiang, H. Selvaraj, Scheduling and Optimal Voltage Selection with Multiple Supply Voltages under Resource Constraints, Integration, the VLSI Journal, vol. 40, no. 2, pp. 174-182, Feb. 2007

26.  D. Selvathi, S. Thamarai Selvi, H. Selvaraj, Abnormality Detection in Brain MR Images Using Minimum Error Thresholding Method, International Journal of Computational Intelligence and Applications (IJCIA), vol. 6, issue 2, 2006

27.  H. Selvaraj, P. Sapiecha, M. Rawski, T. Luba, Functional Decomposition – The Value and Implication for Both Neural Networks and Digital Designing, International Journal of Computational Intelligence and Applications (IJCIA), World Scientific, vol. 6, no. 1, pp. 123-138, 2006

28.  S. Thamarai Selvi, D. Selvathi, H. Selvaraj, R. Ramkumar, Least Squares Support Vector Machine Based Classification of Abnormalities in Brain MR Images, Systems Science, PL ISSN 0137-1223, vol. 32, no. 1, 2006

29.  L. Wang, Y. Jiang, H. Selvaraj, : Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages, The journal of Supercomputing, Springer Science, ISSN: 0920-8542, vol.35, no. 1, January 2006

30.  H. Selvaraj, S. Thamarai Selvi, D. Selvathi, R. Ramkumar, Support Vector Machine Based Automatic Classification of Human Brain Using MR Image Features, International Journal of Computational Intelligence and Applications (IJCIA), World Scientific, vol. 6, no. 3, 2006

31.  M. Rawski, H. Selvaraj, T. Luba, P. Szotkowski, Multilevel Synthesis of Finite State Machines Based on Symbolic Functional Decomposition Concept, International Journal of Computational Intelligence and Applications (IJCIA), World Scientific, vol. 6, issue 2, 2006

32.  M. Rawski, H. Selvaraj, T. Luba, An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices, Journal of Systems Architecture, ELSEVIER, ISSN 1383-7621, vol. 51, no. 6-7, June-July 2005

33.  V. Muthukumar, B. Radhakrishnan, H. Selvaraj, Multiple Voltage and Frequency Scheduling for Power Minimization. Journal of Systems Architecture, ELSEVIER, ISSN 1383-7621, vol. 51, no. 6-7, June-July 2005

34.  J. Li, X. Liang, H. Selvaraj, V. Muthukumar, L. Gewali, A Novel Data Structure for Unit Disk Graphs, The Journal of Combinatorial Mathematics and Combinatorial Computing, pp. 145-156, 2005

35.  L. Wang, Y. Jiang, H. Selvaraj, Multiple Voltage Synthesis Scheme for Low Power Design Under Timing and Resource Constraints, Integrated Computer-Aided Engineering, ISSN: 1069-2509; IOS Press, vol.12, pp. 369-378, 2005

36.  M. Sherwood, L. Gewali, H. Selvaraj, V. Muthukumar, A Fast and Simple Algorithm for Computing m-shortest Paths in State Graph, Systems Science, vol. 30, no. 1, 2004

37.  L. Wang, Y. Jiang, H. Selvaraj, Scheduling and Optimal Voltage Selection with Multiple Supply Voltages under Resource Constraints, VLSI journal's special issue on VLSI System-On-Chip, 2004

38.  H. Selvaraj, P. Sapiecha, T. Luba, Functional Decomposition and its Applications in Design of Digital Circuits and Machine Learning, International Journal of Computational Intelligence and Applications, Imperial College Press, vol. 1, no. 3, pp. 259-271, 2001

39.  H. Selvaraj, P. Sapiecha, An efficiency measure of FPGA based logic synthesis tools, Electronics and Telecommunications Quarterly, PWN, vol. 46, book 4, pp. 497-491, 2000

40.  H. Selvaraj, D.C. Patel, FPGA Based Synthesis Using a Generalised Decomposition Method, International Journal of Electronics, Taylor & Francis Ltd., vol. 78, no. 4, pp. 691-698, 1995

41.  T. Luba, H. Selvaraj, A General Approach to Boolean Function Decomposition and its Applications in FPGA Based Synthesis, VLSI Design, ISSN: 1065-514X, vol. 3, Nos. 3-4, OPA, pp. 289-300, Amsterdam, 1995

42.  K. Jasinki, H. Selvaraj, New Generation Programmable ASIC's architectures and applications, Telecommunication Review, Warsaw, February 1994

43.  H. Selvaraj, A. Czerczak, A Generalised FPGA Based Logic Synthesis Method, Electronics and Telecommunications Quarterly, vol. XXXIX, no. 4, pp. 673-687, 1994

44.  H. Selvaraj, B. Zbierzchowski, Palasm and Cupl - Universal Compilers for Logic Circuits, Telecommunication Review, Warsaw, October 1993

 

Refereed Conference publications

 

1.      G Chmaj, S Sharma, H Selvaraj, Automated Agronomy: Evaluation of Fruits Ripeness Using Machine Learning Approach, 27th International Conference On Systems Engineering, Springer Lecture Notes in Networ and Systems, vol. 182, ISBN 978-3-030-65795-6, pp. 183-191, Dec. 2020.

2.      G. Chmaj, H. Selvaraj, Power usage optimization in multi-UAV common-mission cooperative UAS systems, 26th International Conference on Systems Engineering (ICSEng), Sydney, Australia, IEEE Service Center, ISBN: 978-1-5386-7834-3, 2018.

3.      D. Selvathi, H. Selvaraj, Segmentation of Brain Tumor Tissues in MR Images using Multiresolution Transforms and Random Forest Classifier with ADABOOST Technique, 26th International Conference on Systems Engineering (ICSEng), Sydney, Australia, IEEE Service Center, ISBN: 978-1-5386-7834-3, 2018.

4.      S. Ghimire, H. Selvaraj, A Survey on Bitcoin Cryptocurrency and its Mining, 26th International Conference on Systems Engineering (ICSEng), Sydney, Australia, IEEE Service Center, ISBN: 978-1-5386-7834-3, 2018.

5.      H. A. A. Mansour, A. Khamis, D. Zydek, H. Selvaraj, Performance Analysis and Evaluation of Multi-User Coded Hybrid Spread Spectrum System using Improved Chaotic Sequences, 26th International Conference on Systems Engineering (ICSEng), Sydney, Australia, IEEE Service Center, ISBN: 978-1-5386-7834-3, 2018.

6.      H. A. A. Mansour, A. Khamis, D. Zydek, H. Selvaraj, Statistical Analysis and Performance Comparison of Improved and Optimized CSC using Different Chaotic Maps under Different Fading Channels, 26th International Conference on Systems Engineering (ICSEng), Sydney, Australia, IEEE Service Center, ISBN: 978-1-5386-7834-3, 2018.

7.      H. Selvaraj, N. R. Wanjale, Analog and Mixed-Signal Verification Using Stability Solver on Discretized Models, Proceedings 25th International Conference on Systems Engineering,  Las Vegas, USA, IEEE Computer Society, ISBN-13: 978-1-5386-0610-0, pp. 418-424, 2017.

8.      D. Selvathi, H. Selvaraj, FPGA Implementation for Epileptic Seizure Detection Using Amplitude and Frequency Analysis of EEG Signals, Proceedings 25th International Conference on Systems Engineering,  Las Vegas, USA, IEEE Computer Society, ISBN-13: 978-1-5386-0610-0, pp. 183-192, 2017.

9.      A. Khamis, D. Zydek, H. Selvaraj, Improved Genetic Algorithm for Finite-Horizon Optimal Control of Nonlinear Systems, Proceedings 25th International Conference on Systems Engineering,  Las Vegas, USA, IEEE Computer Society, ISBN-13: 978-1-5386-0610-0, pp. 85-90, 2017.

10.  G. Chmaj, H. Selvaraj, Interconnection Networks Efficiency in System-on-Chip Distributed Computing System: Concentrated and Fat Tree, Proceedings 25th International Conference on Systems Engineering,  Las Vegas, USA, IEEE Computer Society, ISBN-13: 978-1-5386-0610-0, pp. 277-286, 2017.

11.  Gewali, L. P., Sanjeev, K.C., Selvaraj, H. (2016). Estimating Cluster Population, Advances in System Science (vol. 539, pp. 50-60), Cham: Springer. ISBN 978-3-319-48944-5.

12.  Chmaj, G., Selvaraj, H. (2016). In Swiatek, J., Tomczak, J. (Ed.), Layered Reconfigurable Architecture for Autonomous Cooperative UAV Computing Systems, Advances in System Science (vol. 539, pp. 153-163), Cham: Springer. ISBN 978-3-319-48944-5

13.  Khamis, A., Zydek, D., Selvaraj, H. (2016). In Swiatek, J., Tomczak, J. (Ed.), Nonlinear Optimal Control Using Finite-Horizon State Dependent Riccati Equation Combined with Genetic Algorithm, Advances in System Science (vol. 539, pp. 297-307), Cham: Springer. ISBN 978-3-319-48944-5

14.  G. Chmaj, H. Selvaraj, Concentrated mesh and fat tree usage efficiency in System-on-Chip based multiprocessor distributed processing architectures, (MECO), 4th Mediterranean Conference on Embedded Computing; Publisher: IEEE; pp 37-40, ISBN 978-1-4799-8999-7, 2015.

15.  G. Chmaj, H. Selvaraj, Energy-efficient distributed computing solutions for Internet of Things with ZigBee devices, IEEE/ACIS 14th International Conference on Computer and Information Science (ICIS); Publisher: IEEE; pp 437-442, DOI 10.1109/ICIS.2015.7166633, 2015.

16.  G. Chmaj, H. Selvaraj, UAV cooperative data processing using distributed computing platform, 23rd International Conference on Systems Engineering (ICSEng 2014), Las Vegas, USA, Progress in Systems Engineering: Advances in Intelligent Systems and Computing, Springer vol.1089, 2015, pp 455-461, ISBN 978-3-319-08421-3, 2014.

17.  G. Chmaj, H. Selvaraj, Distributed processing applications for Unmanned Aerial Vehicles: a survey, 23rd International Conference on Systems Engineering (ICSEng 2014), Las Vegas, USA, Progress in Systems Engineering: Advances in Intelligent Systems and Computing, vol. 1089, 2015, pp 449-454, ISBN 978-3-319-08421-3, 2014.

18.  L. Daoud, D. Zydek, H. Selvaraj, A Survey on Design and Implementation of Floating Point Adder in FPGA, Progress in Systems Engineering, Progress in Systems Engineering: Advances in Intelligent Systems and Computing, vol. 1089, pp. 885-892, ISBN 978-3-319-08421-3, 2014.

19.  G. Chmaj, H. Selvaraj, L. Gewali, Tracker-node model for energy consumption in reconfigurable processing systems, XVIII International Conference on Systems Science, Advances in Systems Science, Proceedings of ICSS 2013, Springer, 2013, pp. 503-512, doi: 10.1007/978-3-319-01857-7_49

20.  D. Krol, D. Zydek, H. Selvaraj, Matrix Multiplication in Multiphysics Systems Using CUDA, Proceedings of the 18th International Conference on Systems Science (ICSS 2013), Advances in Intelligent Systems and Computing, vol. 240, Springer Verlag, 2014, pp. 493-502, doi: 10.1007/978-3-319-01857-7_48.

21.  L. Daoud, D. Zydek, H. Selvaraj, A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing, Proceedings of the 18th International Conference on Systems Science (ICSS 2013), Advances in Intelligent Systems and Computing, vol. 240, Springer Verlag, 2014, pp. 483-492, doi: 10.1007/978-3-319-01857-7_47.

22.  M. S. Shirazi, B. Morris, H. Selvaraj, Fast FPGA-based fault injection tool for embedded processors, Proceedings of the 14th International Symposium on  Quality Electronic Design (ISQED), pp476-480, 2013

23.  R. Gyawali, L. Gewali, H. Selvaraj, Degree Constrained Triangulation, Proceedings of the 22nd International Conference on Systems Engineering, Coventry, UK, pp. 89-91, 2012

24.  G. Chmaj, D. Zydek, Y. Z. Elhalwagy, H. Selvaraj, Overlay-NoC and H-Phy based computing using Modern Chip MultiProcessors, Proceedings of 2012 IEEE International Conference on Electro/Information Technology (EIT 2012), IEEE Computer Society Press, 2012, pp. 1-6, 2012

25.  B. Kajak, L. Gewali, H. Selvaraj, Ear-Slicing and Quality Triangulation, Proceedings of the 21st International Conference on Systems Engineering, Las Vegas, NV, USA, pp. 194-199, 2011

26.  D. Zydek, G. Chmaj, H. Selvaraj, Extended Analysis of Resource Assignment in Modern Chip Multiprocessors, Proceedings of the 21st International Conference on Systems Engineering, Las Vegas, NV, USA, pp. 457-458, 2011

27.  D. Zydek, H. Selvaraj, L. Gewali, Synthesis of Processor Allocator for Torus-Based Chip MultiProcessors, Proceedings of 7th International Conference on Information Technology: New Generations (ITNG 2010), IEEE Computer Society Press, pp. 13-18, 2010

28.  G. Borowik, M. Rawski, G. Labiak, A. Bukowiec, H. Selvaraj, Efficient Logic Controller Design. Vol. CD, Malaga, Spain, 2010

29.  L. Gewali, V. Roman, H. Selvaraj, Turned Constrained Disjoint Paths, Proceedings of the 20th International Conference on Systems Engineering, Coventry, UK, pp. 150-154, 2009

30.  Lee K.W., Ramasamy K., Singh S.N., H. Selvaraj, Bifurcation to Periodic Orbits in Inferior Olive Neurons, Proceedings of the 20th International Conference on Systems Engineering, Coventry, UK, pp. 306-311, 2009

31.  D. Zydek, H. Selvaraj, L. Gewali, Memory Utilization of Processor Allocator for NoC-based Chip Multiprocessors with Mesh Topology, Proceedings of the 20th International Conference on Systems Engineering, Coventry, UK, pp. 497-502, 2009

32.  D. Zydek, H. Selvaraj, Processor Allocation Problem for NoC-based Chip Multiprocessors, Proceedings of the VI International Conference on Information technology: New Generations, Las Vegas, NV, ISBN 978-0-7695-3596-8, pp. 96-101, 2009

33.  N. Rongratana, L. Gewali, H. Selvaraj, Characterizing Free-Region of Sensor Nodes, Proceedings of the Nineteenth International Conference on Systems Engineering, pp. 375-379, 2008

34.  P. Morawiecki, M. Rawski, H. Selvaraj, Application of Functional Decomposition in Synthesis of Boolean Function Sets, Proceedings International Conference on Systems Engineering ICSEng 2008 pp. 350-355, Las Vegas, NV, USA, 19-21 August, 2008

35.  Szotkowski P., Rawski M., H. Selvaraj, A Graph-Based Approach to Symbolic Functional Decomposition of Finite State Machines, Proceedings International Conference on Systems Engineering ICSEng 2008 pp. 356-361, Las Vegas, NV, USA, 19-21 August, 2008

36.  D. Zydek, N. Shalayan, E. Regentova, H. Selvaraj, Review of Packet Switching Technologies for Future NoC, Proceedings International Conference on Systems Engineering ICSEng 2008, Las Vegas, NV, USA, pp. 306-311, 19-21 August, 2008

37.  B. Surendiran, A. Vadivel, H. Selvaraj, A Soft-Decision Approach for Microcalcification Mass Identification from Digital Mammogram, In Proceedings of World Academy of Science, Engineering and Technology, ISSN 2070-3740, Vol 36, pp. 1236-1240, 2008

38.  P. Morawiecki, M. Rawski, H. Selvaraj, Input Variable Partitioning Method for Functional Decomposition of Functions Specified by Large Truth Tables, Proceedings of the International Conference on Computational Intelligence and Multimedia Applications, vol. 2, pp. 164-168, 2007

39.  P. Ginobbi, W. Vodrazka, J. Wang, H. Selvaraj, N. Ghafoori, M. Trabia, L. Gewali, R. Venkat, College-wide Senior Design Competition: A Motivating Approach, Proceedings of the National Capstone Design Course Conference, Boulder, Co, (CD publication), June, 2007

40.  Min Tun, L. Gewali, H. Selveraj, Interference Aware Routing in Sensor Network, Proceedings of the Fourth International Conference on Information Technology, pp. 140-146, April, 2007

41.  Min Tun, L. Gewali, H. Selveraj, Interference and Backbone Sensor Network, Proceedings of the IASTED Communication Systems and Network, Thailand, pp. 131-136, 2007

42.  M. Rawski, P. Morawiecki, H. Selvaraj, Decomposition of Combinational Circuits Described by Large Truth Tables, ICSE 2006, Coventry, UK, ISBN 978-1-84600-013, pp. 401-406, 2006

43.  D. Mazzella, L. Gewali, H. Selvaraj,, Planning Disjoint Path-Pair of Short Lengths, ICSE 2006, Coventry, UK, ISBN 978-1-84600-013, pp. 265-269, 2006

44.  H. Selvaraj, P. Sapiecha, V. Muthukumar, U. Thirunavukarsu, A. Ramani, Optimizing Supervised Learning of Artificial Neural Network using Functional Decomposition, The 18th Australian Joint Conference on Artificial Intelligence, Sydney, Australia, ISBN -1-86365-715-0, pp. 66-71, 5-9 December, 2005

45.  M. Rawski, H. Selvaraj, T. Luba, P. Szotkowski, Application of Symbolic Functional Decomposition Concept in FSM Implementation targeting FPGA devices, Sixth International Conference on Computational Intelligence and Multimedia Applications, ICCIMA, Las Vegas, NV, pp. 153-158, August 16-18, 2005

46.  M. Rawski, P. Tomaszewicz, H. Selvaraj, T. Luba, Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeting FPGA Architectures, Proceedings Eighth Euromicro Conference on Digital System Design, Architecture, Methods and Tools DSD 2005, Porto, Portugal, IEEE Computer Society, Christophe Wolinski (Editor), pp. 460-466, August 30 - September 3, 2005

47.  H. Selvaraj, P. Tomaszewicz, M. Rawski, T. Luba, Efficient Application of Modern Logic Synthesis in FPGA-Based Designing of Information and Signal Processing Systems, Proceedings International Conference on Information Technology: Coding and Computing, Las Vegas, NV, USA, vol. 2, pp. 22-27, April 4-6, 2005

48.  D. Wen, L. Wang, Y. Jiang, H. Selvaraj, Power optimization for simultaneous scheduling and partitioning with multiple voltages, Proceedings of the 7th WSEAS International Conference on Mathematical Methods and Computational Techniques In Electrical Engineering, Sofia, Bulgaria, ISBN:999-2222-11-X, pp. 156-161, 2005

49.  J. Botwicz, P. Buciak, T. Luba, H. Selvaraj, P. Sapiecha, Aho-Corasick Algorithm Implementation in Hardware For Network Intrusion Detection, Proceedings of IFAC Workshop on Programmable Devices and Systems, PDS 2004, Cracow, pp. 203-207, November 18th-19th, 2004

50.  M. Sherwood, L. Gewali, H. Selvaraj, V. Muthukumar, A Fast and Simple Algorithm for Computing M Shortest Paths in Stage Graph, Proceedings of the XV International Conference On Systems Science XV, Wroclaw, Poland, ISBN 83-7085-805-8, PP.212-218, September 7 - 10, 2004

51.  M. Rawski, H. Selvaraj, P. Morawiecki, Efficient Method of Input Variable Partitioning in Functional Decomposition Based on Evolutionary Algorithms, Proc. Euromicro Symposium on Digital System Design, Architecture, Methods and Tools DSD 2005, Rennes, France, IEEE Computer Society, pp. 136-143, August 31 - September 3, 2004

52.  J. Li, L. Gewali, H. Selvaraj, V. Muthukumar, Hybrid Greedy/Face Routing for Ad-Hoc Sensor Network, DSD 2004, Rennes, France, pp. 574-578, August 31 - September 3, 2004

53.  P. Sapiecha, H. Selvaraj, J. Stanczak, K. Sep, T. Luba, A Hybrid Approach to a Classification Problem, Proceedings of the International IIS: Intelligent Information Processing and Web Mining, Zakopane, Poland, Klopotek M.A., Wierzchon S.T., Trojanowski K. (Eds.), Springer Verlag Lecture Notes in Artificial Intelligence., pp. 99-106, May 17-20, 2004

54.  P. Sapiecha, H. Selvaraj, J. Stanczak, K. Sep, T. Luba, Argument Reduction Methods in Data Mining, Proceedings of the IASTED International Conference Artificial Intelligence and Applications, Innsbruck, Austria, on CD-ROM 411-042, February 16-18, 2004

55.  L. Wang, Y. Jiang, H. Selvaraj, Synthesis Scheme for Low Power Designs with Multiple Supply Voltages by Heuristic Algorithms, Proceedings ITCC, Las Vegas, NV, USA, ISBN 0-7695-2108-8, pp. 826-829, 2004

56.  H. Selvaraj, S. Arivazhagan, L. Ganesan, Fingerprint Verification Using Wavelet Transform, Proceedings ICCIMA’03, Xi’an, China, IEEE Computer Society, ISBN 0-7695-1957-1, pp. 430-435, 27-30 September, 2003

57.  M. Rawski, H. Selvaraj T. Luba, An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices, Proceedings of Euromicro Symposium on Digital System Design, Belek-Antalya, Turkey, pp. 104-110, September 1-6, 2003

58.  M. Pleban, H. Niewiadomski, P. Buciak, H. Selvaraj, P. Sapiecha, T. Luba, NOAH a tool for argument reduction, serial and parallel decomposition of decision tables, Proceedings Euromicro Symposium on Digital Systems Design, Belek-Antalya, Turkey, pp. 248-254, September 1-6, 2003

59.  L. Wang, H. Selvaraj, A scheduling and partitioning scheme for low power circuits, Proceedings Euromicro Symposium on Digital Systems Design, Belek-Antalya, Turkey, pp. 144-147, September 1-6, 2003

60.  L. Wang, Y. Jiang, H. Selvaraj, Scheduling and optimal voltage selection with multiple supply voltages under resource constraints, Proceedings of International Conference on VLSI, Las Vegas, NV, USA, pp. 272-278, June 23-26, 2003

61.  V. Muthukumar, H. Selvaraj, Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation. Proceedings of the Sixteenth International Conference on VLSI Design, New Delhi, India, 2003

62.  B. Radhakrishnan, V. Muthukumar, H. Selvaraj, Multiple Voltage and Frequency Scheduling for Power Minimization, Proceedings of Euromicro Symposium on Digital System Design (DSD) - Architectures, Method and Tools, Belek-Antalya, Turkey, September 1 – 6, 2003

63.  L. Wang, Y. Jiang, H. Selvaraj, V. Muthukumar, A Synthesis Scheme for Low Power Designs with Multiple Voltages under Timing Constraints, Proceedings of the 11th Annual NASA Symposium on VLSI Design, Moscow, ID, USA, 2003

64.  H. Selvaraj, M. Rawski, P. Sapiecha, T. Luba, Functional Decomposition - the Value and Implication for Both Digital Designing and Data Analysis, Proceedings of Fifteenth International Conference on Systems Engineering, Las Vegas, NV, USA, pp. 414 - 420, August, 2002

65.  G. Cherrussery, H. Selvaraj, V. Muthukumar, P. Sapiecha, A Multi-Way Partitioning of Circuit into Multi-FPGAs, Proceedings of Fifteenth International Conference on Systems Engineering, Las Vegas, NV, USA, pp. 429 - 436, August 6-8, 2002

66.  M. Pleban, P. Buciak, H. Niewiadomski, H. Selvaraj, P. Sapiecha, T. Luba, Functional Decomposition Based on Multi-Valued Decision Diagrams, IASTED AIA Malaga, Spain, September, 2002

67.  G. Cherussery, H. Selvaraj, V. Muthukumar, A Bi-level partitioning of a circuit into multi-FPGAs, In the proceedings of Work in Progress Session of the EUROMICRO /DSD conference event in Dortmund, Dortmund, September 4-6, 2002

68.  V. Muthukumar, H. Selvaraj, A Heuristic Algorithm to Variable Partitioning in Functional Decomposition., In the proceedings of Work in Progress Session of the EUROMICRO /DSD conference event in Dortmund, Dortmund, 2002

69.  H. Selvaraj, M. Rawski, T. Luba, FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition, Proceedings of International Conference on Information Technology: Coding and Computing, Las Vegas, NV, USA, IEEE Computer Society, ISBN: 0-7695-1506-1, pp. 355-360, April, 2002

70.  L. Wang, H. Selvaraj, Performance Driven Circuit Clustering and Partitioning, Proc. International Conference on Information Technology: Coding and Computing, Las Vegas, NV, USA, IEEE Computer Society, ISBN: 0-7695-1506-1, pp. 352-354, April, 2002

71.  P. Buciak, T. Luba, H. Niewiadomski, M. Pleban, P. Sapiecha, H. Selvaraj, Decomposition and Argument Reduction of Neural Networks, IEEE Sixth International Conference on Neural Networks and Soft Computing (ICNNSC'02), Zakopane, Poland, June 11-15, 2002

72.  H. Selvaraj, H. Niewiadomski, P. Buciak, M. Pleban, P. Sapiecha, T. Luba, Implementation of Large Neural Networks using Decomposition, International Conference on Mathematics and Engineering Techniques in Medicine and Biological Sciences (METMBS'02), Las Vegas, NV, USA, ISBN 1-892512-31-9, vol. 1, pp. 249-255, June, 2002

73.  E. Regentova, V. Muthukumar, H. Selvaraj, S. Latifi, Integrated Research/Educational Knowledge Base for a New Computer Engineering Curriculum, IASTED International Conference on Computer and Advanced Technology in Education (CATE 2002), Cancun, Mexico, May 20-22, 2002

74.  H. Niewiadomski, P. Buciak, M. Pleban, H. Selvaraj, P. Sapiecha, T. Luba, Decomposition of Large Neural Networks, Proceedings of the IASTED International Conference, Applied Informatics, International Symposium on Artificaial Intelligence and Applications, Insbruck, Austria, ISBN: 0-88986-324-5, pp. 165-170, 2002

75.  T. Luba, H. Niewiadomski, M. Pleban, H. Selvaraj, P. Sapiecha, Functional Decomposition and its Applications in Design of Digital Circuits and Machine Learning, Proceedings of the IASTED, Innsbruck, Austria, ISBN: 0-88986-318-0, ISSN: 1027-2666, pp. 54-59, 2001

76.  H. Selvaraj, H. Niewiadomski, M. Pleban, P. Sapiecha, Decomposition of Digital Circuits and Neural Networks, Special Sessions on Modern Digital System Synthesis at The Fifth Multi-Conference on Systemics, Cybernetics and Informatics - SCI'2001, Orlando, USA., pp. 302-307

77.  M. Venkatesan, R.J. Bignall, H. Selvaraj, An Improved Representation of Functions for Partition Based Functional Decomposition, ICCIMA’01, Japan, IEEE Computer Society, ISBN 0-7695-1312-3, pp. 373

78.  H. Selvaraj, P. Sapiecha, N. Dhavlikar, Partitioning of Large HDL ASIC Designs into Multiple FPGA Devices for Prototyping and Verification, ICCIMA’01, Japan, IEEE Computer Society, ISBN 0-7695-1312-3, pp. 411-416

79.  M. Venkatesan, R.J. Bignall, H. Selvaraj, A Variable Partition Approach for Disjoint Decomposition, ISCAS'01, Sydney, Australia., ISBN 0-7803-6685-9, pp. 157-162

80.  M. Venkatesan, R.J. Bignall, H. Selvaraj, An Efficient Input-Output Encoding Approach for Serial Decomposition, SBCCI'00, Brazil, ISBN 0-7695-0843-x

81.  P. Sapiecha, H. Selvaraj, M. Pleban, Decomposition of Boolean Relations and Functions in Logic Synthesis and Data Analysis, Proceedings of the Second International Conference on Rough Sets and Current Trends in Computing, Banff, Canada, ISBN 0-7731-0413-5, pp. 449-456, 2000

82.  M. Venkatesan, B. Bignall, H. Selvaraj, An Improved Column Compatibility Approach for Partition based Functional Decomposition, Euromicro-2000, Maastricht, The Netherlands, pp. 67-73, 2000

83.  H. Selvaraj, B. Li, A Parameter to Measure the Efficiency of FPGA based Logic Synthesis Tools, Euromicro-2000, Maastricht, The Netherlands, pp. 212-218, 2000

84.  H. Selvaraj, M.Venkatesan, B. Bignall, B. Verma, Functional Decomposition for FPGA Based Designs: A Weighted Graph Approach for Encoding of Compatible Classes, International Conference on Computational Intelligence and Multimedia Applications, New Delhi, India, IEEE Computer Society, ISBN: 0-7695-0300-4, pp. 217-222, 1999

85.  B. Verma, P. Sharma, S. Kulkarni, H. Selvaraj, An Intelligent On-Line System for Content Based Image Retrieval, International Conference on Computational Intelligence and Multimedia Applications, New Delhi, India, IEEE Computer Society, ISBN: 0-7695-0300-4, pp. 273-277, 1999

86.  H. Selvaraj, V. Muthukumar, A Reconfigurable Printed Character Recognition System Using A Logic Synthesis Tool, Euromicro, Sweden, IEEE Computer Society, ISBN 0-8186-8646-4, pp. 24-29, 1998

87.  H. Selvaraj, M. Nowicka, T. Luba, Decomposition Strategies and their Performance in FPGA-based Technology Mapping, 11th International Conf. On VLSI Design, Chennai, India, IEEE Computer Science, ISBN 0-8186-8224-8, pp. 388-393, 1998

88.  M. Venkatesan, H. Selvaraj, B. Bignall, Character Recognition Using Functional Decomposition, International Conference on Computational Intelligence and Multimedia Applications, Churchill, Australia, World Scientific, ISBN 981-02-3352-3, pp. 721-726, 1998

89.  M. Nowicka, T. Luba, H. Selvaraj, Multilevel Decomposition Strategies in Decomposition-Based Algorithms and Tools, IFIP Workshop on Logic and Architecture Synthesis, Grenoble, France, pp. 129-136, 1997

90.  M. Venkatesan, H. Selvaraj, B. Bignall, Parallel Decomposition of Multiple Valued Functions and its applications in Information Systems, International Conference on Computational Intelligence and Multimedia Applications, Gold Coast, Australia, pp. 112-116, 1997

91.  H. Selvaraj, T. Luba, B. Bignall, M. Venkatesan, Disjoint Serial Decomposition Using Variable Rejection, IFIP Workshop on Logic and Architecture Synthesis, Grenoble, France, pp. 69-76, 1996

92.  M. Venkatesan, H. Selvaraj, B. Bignall, Parallel Decomposition of Binary Valued Functions - Selection of Dependent Inputs by Elimination of Contradictions, IFIP Workshop on Logic and Architecture Synthesis, Grenoble, France, pp. 303-310, 1996

93.  H. Selvaraj, T. Luba, Information System decomposition, Eighth Australian Joint Artificial Intelligence Conference, Poster Proceedings, Canberra, p113, 1995

94.  H. Selvaraj, T. Luba, A Balanced Multilevel Decomposition Method, The European Design and Test Conference ED & TC '95, Paris, France, IEEE Computer Society Press, pp. 594

95.  T. Luba, H. Selvaraj, A. Krasniewski, A New Approach to FPGA Based Logic Synthesis, European Workshop on Design Methodologies for Microelectronics and Signal Processing, Gliwice-Cracow, pp. 135-142, 1993

96.  H. Selvaraj, A. Czerczak, A. Krasniewski, T. Luba, A Generalised Decomposition of Boolean Functions and its Application in FPGA Based Synthesis, IFIP Workshop on Logic and Architecture Synthesis, Grenoble, France, pp. 147-166, 1993

97.  H. Selvaraj, B. Zbierzchowski, Palasm and Cupl - Universal Compilers for Logic Circuits, National Symposium on Telecommunication, Bydgoszcz, October, 1993

 

Other Publications, Prefaces, Introductions, Invited Talks

1.      H. Selvaraj, S. Arivazhagan, Editorial: Applications of Computational Intelligence. International Journal of Computational Intelligence and Applications (IJCIA) 8(2), 2009)

2.      Inaugural address, International Conference on Computing Technologies, Sivakasi, India, Dec. 2009.

3.      Key Note address: “Multicore Processor Technologies”, International Conference on Computing Technologies, Sivakasi, India, Dec. 2009.

4.      Inaugural address, ICCIMA 2007, Sivakasi, India, December 2007.

5.      Communication Trends, Key note, National Seminar, India, Dcember 2007.

6.      H. Selvaraj, M. Nowicka, T. Luba: Decomposition Strategies and their Performance in FPGA-based Technology Mapping, Research Report 13/96, Monash Univ., 1997.

7.      H. Selvaraj, R.J. Bignall, M. Venkatesan, Selection of Candidate Variables for Disjoint Serial Decomposition, Research Report 10/96, GSCIT, Monash University, 1996. 

8.      H. Selvaraj, T. Luba, M. Nowicka, R.J. Bignall, Functional Decomposition Using Graph Colouring Heuristics, Research Report 13/96, GSCIT, Monash University, 1996.

9.      M. Venkatesan, H. Selvaraj, R.J.Bignall, Parallel Decomposition of Binary Valued Functions-Selection of Dependent Inputs by Elimination of Contradictions, Information Technology Research, RR12/96, IT Research Center, Monash University, 1996. 

 

Exhibition

EURO-DAC'94 Grenoble: DECMAIN software for FPGA based Logic Synthesis.

 

Honors

1.      Outstanding Department Chair award, UNLV, 2012.

2.      Professor of the Year Award, Department of Electrical and Computer Engineering, selected by undergraduate students, 2010.

3.      Outstanding Mentor Award, Graduate & Professional Student Association, UNLV, 2010.

4.      “Eminent Engineer”, Tau Beta Pi, May 2009.

5.      UNLV Alumni Student Centered Faculty Award for 2002.

6.      1994 - Distinction award for Ph.D. from the Warsaw University of Technology

7.      1990 - Polish Government Scholarship for Ph.D.

8.      1986 - Letter of Merit from the Minister of Higher Education, Government of Poland

9.      1984 - Copernicus Best Student Award from the Ministry of Higher Education, Government of Poland

10.  1977 – India\Poland Government scholarship for undergraduate engineering degree

 

Other major creative works

1.      Synthesis, Analysis, Testing and Self-testing Methods for Digital Circuits. Project No. 3 0633 91 01 of the State Committee for Scientific Research (KBN), Republic of Poland.

2.      Multiple Criterion Design of Digital Circuits. Project No. 8s504 005 of the State Committee for Scientific Research (KBN), Republic of Poland.

3.      ASIC for Telecommunications. Project No. 8 8413 9203 of the State Committee for Scientific Research (KBN), Republic of Poland.

 

Please contact Dr Henry Selvaraj for information on funded projects and grants.